As shown in FIG. 25, a microprocessor, its peripheral LSI, and the like have a number of output buffers OB for outputting an address signal and a data signal. A 16 bit microprocessor has, for example, 20 output buffers for outputting an address/data signal. Examples of the internal circuit of each output buffer OB are shown in FIGS. 26 and 27. Each output buffer OB is controlled by a timing signal T to output an address/data signal supplied from a bus BUS such as an address bus and data bus. When an address/data signal is outputted, one of two transistors (P-MOS transistor Tr1 and N-MOS transistor Tr2 in FIG. 26, or N-MOS transistors Tr3 and Tr4 in FIG. 27) connected in series between high and low power sources turns on and the other turns off. When an inverted signal is outputted from the output buffer OB, the on/off state of the two transistors is reversed. If both two transistors turn on momentarily at the same time during the transient state while the state of the two transistors is reversed, a through current will flow via the two transistors between the high and low power source terminals. FIG. 28 shows a through current flowing in the output buffer OB shown in FIG. 26 when an output signal is inverted. As seen from FIG. 26, a through current will flow at time t1 and time t2 when an output of the output buffer is inverted from "1" to "0" and from "0" to "1", respectively. The output buffers OB are all controlled by the same timing signal T, so that a through current may flow through a plurality of output buffers OB at the same time. The total through current may take a value in the order of ampere. Thus, the potential of the internal power source line changes greatly resulting in a possible malfunction.
Furthermore, a number of output buffers OB shown in FIG. 25 operate in response to the same timing signal as described above. Therefore, for example, if many of output buffers change its output level from "H" level to "L" level, a rush current flowing through the ground pin (GND) of the semiconductor integrated circuit takes a value in the order of ampere. Thus, the potential (internal power source potential) at the ground pin rises, resulting in a malfunction. FIG. 29 illustrates a rise of the ground (GND) potential when all output buffers OB change its output level from "1" level to "0" level.
According to the background art, the timing signal is supplied via delay means DL to each output buffer OB in order to prevent the ground potential from rising, as seen from FIG. 30. Therefore, as shown in FIG. 31, the operation timings of the output buffers OB are shifted sequentially so that the total current flowing at any timing can be suppressed to a small value.
The above method using the delay means is however associated with the following disadvantage. Specifically, the pulse width of the timing signal T is generally the same as that of the main clock used within the LSI, so that sometimes an output pulse may not be obtained from the timing signal after it has passed through the delay means. This case will be described with reference to FIGS. 32 to 34. FIG. 32 shows an example of a delay means, FIG. 33 illustrate a normal state where a pulse is outputted, and FIG. 34 illustrates an abnormal state where a pulse is not outputted. If a pulse indicated at "A" in FIG. 33 is applied to the input IN of the delay means shown in FIG. 32, there are obtained pulses indicated at "B" and "C" in FIG. 33 at the circuit portions shown in FIG. 32, and finally a pulse indicated at "D" in FIG. 33. In FIG. 33 a delay time is represented by DT. If the input pulse width is narrowed so as to speed up the operation time as seen from FIG. 34, there is obtained no pulse as indicated at "D" in FIG. 34. In other words, if delay means are used, it is not possible to make high the operation frequency (speed) of a semiconductor integrated circuit.
As described above, according to the background art, there is a possibility of a malfunction because of a through current flowing into an output buffer when an output level is inverted. There is also a possibility of a malfunction if many output buffers operate at the same time in response to the same timing signal. In order to eliminate the effect of such simultaneous operations, the operation timings for output buffers may be shifted. However, in this case, it is not possible to make high the operation speed. Namely, the influence of power source noises has not been effectively suppressed heretofore.